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add the manual Intel's way to query cache info
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Gael Guennebaud
parent
931027f31b
commit
5e7bd967cc
@ -40,7 +40,9 @@ int main()
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string[1] = abcd[3];
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string[2] = abcd[2];
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string[3] = 0;
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cout << endl;
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cout << "vendor id = " << string_char << endl;
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cout << endl;
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// dump Intel direct method
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{
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@ -69,7 +71,91 @@ int main()
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cache_id++;
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} while(cache_type>0);
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}
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// manual method for intel
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{
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l1 = l2 = l3 = 0;
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abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;
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EIGEN_CPUID(abcd,0x00000002,0);
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unsigned char * bytes = reinterpret_cast<unsigned char *>(abcd)+2;
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for(int i=0; i<14; ++i)
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{
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switch(bytes[i])
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{
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case 0x0A: l1 = 8; break; // 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines
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case 0x0C: l1 = 16; break; // 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines
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case 0x0E: l1 = 24; break; // 0Eh data L1 cache, 24 KB, 6 ways, 64 byte lines
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case 0x10: l1 = 16; break; // 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
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case 0x15: l1 = 16; break; // 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
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case 0x2C: l1 = 32; break; // 2Ch data L1 cache, 32 KB, 8 ways, 64 byte lines
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case 0x30: l1 = 32; break; // 30h code L1 cache, 32 KB, 8 ways, 64 byte lines
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// 56h L0 data TLB, 4M pages, 4 ways, 16 entries
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// 57h L0 data TLB, 4K pages, 4 ways, 16 entries
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// 59h L0 data TLB, 4K pages, fully, 16 entries
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case 0x60: l1 = 16; break; // 60h data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored
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case 0x66: l1 = 8; break; // 66h data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored
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case 0x67: l1 = 16; break; // 67h data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored
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case 0x68: l1 = 32; break; // 68h data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored
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// 77h code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64)
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// 96h data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64)
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case 0x1A: l2 = 96; break; // code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64)
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case 0x22: l3 = 512; break; // code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored
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case 0x23: l3 = 1024; break; // code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x25: l3 = 2048; break; // code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x29: l3 = 4096; break; // code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x39: l2 = 128; break; // code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored
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case 0x3A: l2 = 192; break; // code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored
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case 0x3B: l2 = 128; break; // code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored
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case 0x3C: l2 = 256; break; // code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored
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case 0x3D: l2 = 384; break; // code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored
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case 0x3E: l2 = 512; break; // code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored
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case 0x40: l2 = 0; break; // no integrated L2 cache (P6 core) or L3 cache (P4 core)
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case 0x41: l2 = 128; break; // code and data L2 cache, 128 KB, 4 ways, 32 byte lines
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case 0x42: l2 = 256; break; // code and data L2 cache, 256 KB, 4 ways, 32 byte lines
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case 0x43: l2 = 512; break; // code and data L2 cache, 512 KB, 4 ways, 32 byte lines
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case 0x44: l2 = 1024; break; // code and data L2 cache, 1024 KB, 4 ways, 32 byte lines
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case 0x45: l2 = 2048; break; // code and data L2 cache, 2048 KB, 4 ways, 32 byte lines
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case 0x46: l3 = 4096; break; // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines
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case 0x47: l3 = 8192; break; // code and data L3 cache, 8192 KB, 8 ways, 64 byte lines
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case 0x48: l2 = 3072; break; // code and data L2 cache, 3072 KB, 12 ways, 64 byte lines
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case 0x49: l3 = 4096; break; // code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or
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case 0x4A: l3 = 6144; break; // code and data L3 cache, 6144 KB, 12 ways, 64 byte lines
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case 0x4B: l3 = 8192; break; // code and data L3 cache, 8192 KB, 16 ways, 64 byte lines
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case 0x4C: l3 = 12288; break; // code and data L3 cache, 12288 KB, 12 ways, 64 byte lines
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case 0x4D: l3 = 16384; break; // code and data L3 cache, 16384 KB, 16 ways, 64 byte lines
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case 0x4E: l2 = 6144; break; // code and data L2 cache, 6144 KB, 24 ways, 64 byte lines
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case 0x78: l2 = 1024; break; // code and data L2 cache, 1024 KB, 4 ways, 64 byte lines
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case 0x79: l2 = 128; break; // code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x7A: l2 = 256; break; // code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x7B: l2 = 512; break; // code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x7C: l2 = 1024; break; // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored
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case 0x7D: l2 = 2048; break; // code and data L2 cache, 2048 KB, 8 ways, 64 byte lines
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case 0x7E: l2 = 256; break; // code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64)
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case 0x7F: l2 = 512; break; // code and data L2 cache, 512 KB, 2 ways, 64 byte lines
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case 0x80: l2 = 512; break; // code and data L2 cache, 512 KB, 8 ways, 64 byte lines
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case 0x81: l2 = 128; break; // code and data L2 cache, 128 KB, 8 ways, 32 byte lines
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case 0x82: l2 = 256; break; // code and data L2 cache, 256 KB, 8 ways, 32 byte lines
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case 0x83: l2 = 512; break; // code and data L2 cache, 512 KB, 8 ways, 32 byte lines
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case 0x84: l2 = 1024; break; // code and data L2 cache, 1024 KB, 8 ways, 32 byte lines
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case 0x85: l2 = 2048; break; // code and data L2 cache, 2048 KB, 8 ways, 32 byte lines
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case 0x86: l2 = 512; break; // code and data L2 cache, 512 KB, 4 ways, 64 byte lines
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case 0x87: l2 = 1024; break; // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines
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case 0x88: l3 = 2048; break; // code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64)
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case 0x89: l3 = 4096; break; // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64)
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case 0x8A: l3 = 8192; break; // code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64)
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case 0x8D: l3 = 3072; break; // code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64)
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case 0x9B: l2 = 1024; break; // data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64)
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default: break;
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}
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}
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cout << endl;
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cout << "tedious way l1 = " << l1 << endl;
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cout << "tedious way l2 = " << l2 << endl;
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cout << "tedious way l3 = " << l3 << endl;
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}
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// dump everything
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std::cout << endl <<"Raw dump:" << endl;
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@ -94,36 +180,3 @@ int main()
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#endif
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return 0;
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}
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#if 0
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#define FOO(CODE) { \
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EIGEN_CPUID(abcd, CODE); \
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std::cout << "The code " << CODE << " gives " \
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<< (int*)(abcd[0]) << " " << (int*)(abcd[1]) << " " \
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<< (int*)(abcd[2]) << " " << (int*)(abcd[3]) << " " << std::endl; \
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}
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int abcd[5];
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abcd[4] = 0;
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// for (int a = 0; a < 5; a++) {
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// cpuid(abcd,a);
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// std::cout << "The code " << a << " gives "
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// << abcd[0] << " " << abcd[1] << " "
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// << abcd[2] << " " << abcd[3] << " " << abcd[4] << std::endl;
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// }
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FOO(0x1); std::cerr << (char*)abcd << "\n";
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FOO(0x2);
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FOO(0x2);
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FOO(0x2);
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FOO(0x3); std::cerr << (char*)abcd << "\n";
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FOO(0x80000002); std::cerr << (char*)abcd << "\n";
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FOO(0x80000003); std::cerr << (char*)abcd << "\n";
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FOO(0x80000004); std::cerr << (char*)abcd << "\n";
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FOO(0x80000005); std::cerr << (char*)abcd << "\n";
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FOO(0x80000006); std::cerr << (char*)(abcd) << "\n";
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std::cerr << "L2 : " << (abcd[2] >> 16) << "KB\n";
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// FOO(0x80000019); std::cerr << (char*)(abcd) << "\n";
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FOO(0x8000001A); std::cerr << (char*)(abcd) << "\n";
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#endif
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