Mehdi Goli 16a56b2ddd [SYCL] This PR adds the minimum modifications to Eigen core required to run Eigen unsupported modules on devices supporting SYCL.
* Adding SYCL memory model
* Enabling/Disabling SYCL  backend in Core
*  Supporting Vectorization
2019-06-27 12:25:09 +01:00
..
2019-03-14 10:08:12 +01:00
2016-05-18 14:03:03 +02:00
2019-05-31 14:08:34 -07:00
2018-11-23 15:37:09 +01:00
2019-06-20 11:47:49 -07:00
2019-01-15 10:51:03 +01:00
2018-11-23 15:12:06 +01:00